module fifo_selector (
    input wire clk,
    input wire rst_n,
    input wire we,
    //input wire re,
    input wire ram0_empty,
    input wire ram1_empty,
    input wire ram2_empty,
    input wire [7:0] ram0_burst_len,
    input wire [7:0] ram1_burst_len,
    input wire [7:0] ram2_burst_len,
    output reg [1:0] current_ram
    //output reg [1:0] read_ram
);

    // 状态定义
    localparam RAM0_C = 2'b00;
    localparam RAM1_B = 2'b01;
    localparam RAM2_A = 2'b10;
    localparam IDLE   = 2'b11;

    // 写状态机
    reg [7:0] write_counter;
    reg [7:0] current_write_target;

/*     // 读状态机
    reg [7:0] read_counter;
    reg [7:0] current_read_target;
    reg read_active;
 */
    // 写状态机
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            current_ram <= RAM0_C;
            write_counter <= 8'd0;
            current_write_target <= ram0_burst_len;
        end else begin
            case (current_ram)
                RAM0_C: begin
                    if (we) begin
                        if (write_counter == current_write_target - 1) begin
                            current_ram <= RAM1_B;
                            write_counter <= 8'd0;
                            current_write_target <= ram1_burst_len;
                        end else begin
                            write_counter <= write_counter + 1;
                        end
                    end
                end
                
                RAM1_B: begin
                    if (we) begin
                        if (write_counter == current_write_target - 1) begin
                            current_ram <= RAM2_A;
                            write_counter <= 8'd0;
                            current_write_target <= ram2_burst_len;
                        end else begin
                            write_counter <= write_counter + 1;
                        end
                    end
                end
                
                RAM2_A: begin
                    if (we) begin
                        if (write_counter == current_write_target - 1) begin
                            current_ram <= IDLE;
                            write_counter <= 8'd0;
                        end else begin
                            write_counter <= write_counter + 1;
                        end
                    end
                end
                
                IDLE: begin
                    // 等待下一次传输
                    if (we) current_ram <= RAM0_C;
                end
                
                default: current_ram <= RAM0_C;
            endcase
        end
    end

    /* // 读状态机
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            read_ram <= RAM0_C;
            read_counter <= 8'd0;
            read_active <= 1'b0;
        end else begin
            if (re && !read_active) begin
                // 确定从哪个FIFO开始读
                if (!ram0_empty) read_ram <= RAM0_C;
                else if (!ram1_empty) read_ram <= RAM1_B;
                else if (!ram2_empty) read_ram <= RAM2_A;
                read_active <= 1'b1;
                read_counter <= 8'd0;
                
                // 设置当前读取目标长度
                case (read_ram)
                    RAM0_C: current_read_target <= ram0_burst_len;
                    RAM1_B: current_read_target <= ram1_burst_len;
                    RAM2_A: current_read_target <= ram2_burst_len;
                    default: current_read_target <= ram0_burst_len;
                endcase
            end
            else if (read_active && re) begin
                if (read_counter == current_read_target - 1) begin
                    read_active <= 1'b0;
                    read_counter <= 8'd0;
                end else begin
                    read_counter <= read_counter + 1;
                end
            end
        end
    end */

endmodule